#ifndef __STM32F103_REG_H
#define __STM32F103_REG_H


#include "main.h"


typedef struct
{
  volatile uint32_t CR;
  volatile uint32_t CFGR;
  volatile uint32_t CIR;
  volatile uint32_t APB2RSTR;
  volatile uint32_t APB1RSTR;
  volatile uint32_t AHBENR;
  volatile uint32_t APB2ENR;
  volatile uint32_t APB1ENR;
  volatile uint32_t BDCR;
  volatile uint32_t CSR;

#ifdef STM32F10X_CL  
  volatile uint32_t AHBRSTR;
  volatile uint32_t CFGR2;
#endif /* STM32F10X_CL */ 

#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)   
  uint32_t RESERVED0;
  volatile uint32_t CFGR2;
#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ 
} RCC_TypeDef;


typedef struct
{
  volatile uint32_t CRL;
  volatile uint32_t CRH;
  volatile uint32_t IDR;
  volatile uint32_t ODR;
  volatile uint32_t BSRR;
  volatile uint32_t BRR;
  volatile uint32_t LCKR;
} GPIO_TypeDef;

typedef struct
{
  volatile uint32_t SR;    /*!< USART Status register, Address offset: 0x00 */
  volatile uint32_t DR;    /*!< USART Data register,   Address offset: 0x04 */
  volatile uint32_t BRR;   /*!< USART Baud rate register, Address offset: 0x08 */
  volatile uint32_t CR1;   /*!< USART Control register 1, Address offset: 0x0C */
  volatile uint32_t CR2;   /*!< USART Control register 2, Address offset: 0x10 */
  volatile uint32_t CR3;   /*!< USART Control register 3, Address offset: 0x14 */
  volatile uint32_t GTPR;  /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;

typedef struct
{
  volatile uint32_t ACR;
  volatile uint32_t KEYR;
  volatile uint32_t OPTKEYR;
  volatile uint32_t SR;
  volatile uint32_t CR;
  volatile uint32_t AR;
  volatile uint32_t RESERVED;
  volatile uint32_t OBR;
  volatile uint32_t WRPR;
#ifdef STM32F10X_XL
  uint32_t RESERVED1[8]; 
  volatile uint32_t KEYR2;
  uint32_t RESERVED2;   
  volatile uint32_t SR2;
  volatile uint32_t CR2;
  volatile uint32_t AR2; 
#endif /* STM32F10X_XL */  
} FLASH_TypeDef;

/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
  memory mapped structure for SysTick
  @{
 */
typedef struct
{
  volatile uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
  volatile uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
  volatile uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
  volatile const uint32_t CALIB;                  /*!< Offset: 0x0C  SysTick Calibration Register        */
} SysTick_Type;

/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
  @{
 */
typedef struct
{
  volatile uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */
       uint32_t RESERVED0[24];                                   
  volatile uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */
       uint32_t RSERVED1[24];                                    
  volatile uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */
       uint32_t RESERVED2[24];                                   
  volatile uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */
       uint32_t RESERVED3[24];                                   
  volatile uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */
       uint32_t RESERVED4[56];                                   
  volatile uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
       uint32_t RESERVED5[644];                                  
  volatile const uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */
}  NVIC_Type;

/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
  memory mapped structure for System Control Block (SCB)
  @{
 */
typedef struct
{
  volatile const  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
  volatile uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
  volatile uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */
  volatile uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
  volatile uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
  volatile uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
  volatile uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
  volatile uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
  volatile uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */
  volatile uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */
  volatile uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
  volatile uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */
  volatile uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */
  volatile uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */
  volatile const uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */
  volatile const uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */
  volatile const uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */
  volatile const uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */
  volatile const uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */
} SCB_Type;   


#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */

/*!< Peripheral memory map */
#define APB1PERIPH_BASE       PERIPH_BASE
#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)

#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)

#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)


#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)

#define USART1              ((USART_TypeDef *) USART1_BASE)


#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)

#define RCC                 ((RCC_TypeDef *) RCC_BASE)

#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */

#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

/* Memory mapping of Cortex-M3 Hardware */
#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */

#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */



#endif

